Pipelining and bypassing in a VLIW processor

2) Sparc2 was programmed in C , a high-level language, and MARS was programmed in assembly language, which made full use of the hardware features of the MARS processors like bit field extraction and manipulation, table access, and interprocessor communication support. The key contribution of this short note is the partitioning of the Goldberg-Tarjan network flow algorithm for pipelined execution on a message-passing multicomputer. The MARS multicomputer is the platform used in the implementation. Although 15 processors were available in MARS, the granularity of the algorithm needed to maintain maximal data locality permitted the use of only six processors. A larger number of processors would have required data duplication and more interprocessor communication. Even in the present implementation, copies of the vertex labels are maintained in tables in three PE memories. This forced the algorithm to be partitioned into two phases, thus reducing the efficiency. A serial implementation of the entire algorithm on a single PE of the MARS system was impossible. because of the limited size of the program memory within each PE. Although the exact CPU time of this implementation could not be measured, a six-processor version at 5 MHz yields the same order of performance as a Sparc2 workstation at 40 MHz. Many data partitioning-based implementations of the same algorithm exist IS], [7]. Ours is the first attempt at an algorithm-based partitioning approach. The pipelined implementation can be made even faster by using a hybrid pipelined-parallel approach that uses many PE's in parallel within the pipelined stages. Other methods of combining data partitioning and pipelining may improve the efficiency of either implementation. Further studies may investigate such combinations. Experiments with the push-relabel method for the maximum flow problem on a connection machine, " DI-Analysis of preflow push algorithms for maximum network flow, " SIAM J. [8] A. V. Kwzanov, " Determining the maximum flow in a network by the method of preflows, " Soviet Math. Abstract-This short note describes issues involved in the bypassing mechanism for a very long instruction word (VLIW) processor and its relation to the pipeline structure of the processor. We will first describe the pipeline structure of our processor and analyze its performance and compare it to typical RISC-style pipeline structures given the context of a processor with multiple functional units. Next we shall study the performance effects of various bypassing schemes in terms of their effectiveness in resolving pipeline data hazards and …